1. Field of the Invention
The present invention relates to a semiconductor device constituted of stacked semiconductor chips, adopting a Chip on Chip technology or the like.
2. Description of the Related Art
In recent years, a volume of data handled in system products such as mobile phones have dramatically increased. In accordance with this increase, capacities of semiconductor memories mounted in the system products have also increased and there has arisen a demand for semiconductor memories with a high data transfer rate. Generally, as a semiconductor device mounted in a system product of this type, there has been provided a System on Chip (SoC) in which a logic (controller) and memories are integrated on one chip, and a System in Package (SiP) in which a logic chip and a memory chip are stacked and sealed in one package. A semiconductor process of the SoC is complicated and also costs high. On the other hand, the SiP is formed by packaging a plurality of semiconductor chips each of which is manufactured by using an existing semiconductor process, and thus does not require the development of a new semiconductor process and is relatively low in manufacturing cost. Therefore, system products using the SiP have recently been on an increasing trend.
Further, a Chip on Chip (CoC) technology which connects chips by micro-bumps or the like in order to reduce a parasitic LCR and to increase a data transfer rate has been increasingly adopted for the SiP, as disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2005-39160, Japanese Unexamined Patent Application Publication No. 2005-39161, Japanese Unexamined Patent Application Publication No. 2005-109419, Japanese Unexamined Patent Application Publication No. 2000-332192, Japanese Unexamined Patent Application Publication No. 2001-94037, and Japanese Unexamined Patent Application Publication No. Sho 61-42942.
In the CoC, when chips are connected to each other by micro-bumps or the like, element formed surfaces are made to face each other in most cases in order to reduce the parasitic LCR to the minimum. In this case, after the CoC is assembled, a surface of a semiconductor chip with a smaller chip size (small chip) is covered with a semiconductor chip with a larger chip size (large chip). This does not allow the direct connection of external terminals of the small chip to external terminals of a semiconductor device. Therefore, it is not possible to test the small chip alone if not through the large chip. Further, it is not possible to supply power to the small chip if not through the large chip.